In-line device turnaround time - E1.20 RDM (Remote Device Management) Protocol Forums

sjackman · April 29th, 2010

If the turnaround logic is implemented in software, I agree that the implementation should drop the first preamble byte. If the turnaround logic is implemented in hardware (logic, PLD or FPGA), the first bit can be shortened by a very small amount, and it's not necessary to drop the first preamble byte. It would be helpful to define that very small amount in the spec.

It should be possible to shorten one bit up to 50% and the UART should still be able to recover it. 7.5% shouldn't be any problem. Most UARTs sample each bit 16 times. If the bit is shortened by 7.5%, the UART would see 15 low samples and one high sample, well within tolerance.

Cheers,
Shaun

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April 29th, 2010	#7
sjackman Task Group Member Join Date: Sep 2006 Posts: 26	If the turnaround logic is implemented in software, I agree that the implementation should drop the first preamble byte. If the turnaround logic is implemented in hardware (logic, PLD or FPGA), the first bit can be shortened by a very small amount, and it's not necessary to drop the first preamble byte. It would be helpful to define that very small amount in the spec. It should be possible to shorten one bit up to 50% and the UART should still be able to recover it. 7.5% shouldn't be any problem. Most UARTs sample each bit 16 times. If the bit is shortened by 7.5%, the UART would see 15 low samples and one high sample, well within tolerance. Cheers, Shaun