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| RDM Timing Discussion Discussion and questions relating to the timing requirements of RDM. |
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May 22nd, 2009
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#5 |
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Junior Member
Join Date: Feb 2009
Posts: 13
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With the exception of the break and MAB timing the FTDI and SiLabs chips have large enough FIFO's that for most RDM packets the inter-slot time would be zero as long as your USB driver can push the data down the USB lpipe in large enough chunks.
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